• DocumentCode
    846562
  • Title

    Safe design for TF-SOI power MOSFETs

  • Author

    Roig, J. ; Stefanov, E. ; Morancho, F.

  • Author_Institution
    Lab. d´´Analyse et d´´Archit. des Systemes, CNRS, Toulouse, France
  • Volume
    42
  • Issue
    4
  • fYear
    2006
  • Firstpage
    245
  • Lastpage
    247
  • Abstract
    The aim of the work reported is to establish new design restrictions for thin-film silicon-on-insulator (TF-SOI) power MOSFETs using an analytical closed form expression to obtain the electric field at the gate edge. When the gate oxide is extended above the drift region, this field becomes stronger, thus degrading device performance and reliability.
  • Keywords
    power MOSFET; semiconductor device models; silicon-on-insulator; thin film transistors; TF-SOI power MOSFET; analytical closed form expression; drift region; gate edge field; gate oxide; thin-film silicon-on-insulator power MOSFET;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20063220
  • Filename
    1599655
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=846562