Two new techniques for unit-delay compiled simulation

The potential change (PC)-set method and the parallel technique for generating compiled unit-delay simulators for acrylic circuits are discussed. The PC-set method analyzes the network, determines the set of potential change times for each net, and generates gate simulations for each potential change. The parallel technique, which is based on the concept of bit-parallel simulation is faster and generates less code than the PC-set method, but it is not amenable to data-parallel simulation of multiple input vectors. Both techniques are based on the well-known levelization algorithm used to generate zero-delay levelized compiled code simulation. Two optimizations of the basic parallel technique are presented, called bit-field trimming and shift elimination. Performance results using the ISCAS 85 benchmarks show a factor-of-four improvement for the PC-set method and a factor-of-ten improvement for the parallel technique. The optimization schemes show an average performance improvement of 47% over the unoptimized simulations