DocumentCode
849347
Title
Comments, with reply, on ´Dual-gate operation and volume inversion in n-channel SOI MOSFETs´ by S. Venkatesan et al
Author
Balestra, F.
Author_Institution
Lab. de Physique des Composant a Semicond., CNRS, Grenoble, France
Volume
13
Issue
12
fYear
1992
Firstpage
658
Lastpage
660
Abstract
For original paper see ibid., vol.13, no.1, pp.44-6 (Jan. 1992). The commenter disagrees with the suggestion by S. Venkatesan, et al. that dual-channel volume inverted devices do not offer significant current-enhancement advantages, other than that expected from the second channel, over the conventional single-channel devices for silicon thicknesses in the 0.1- mu m range. The commenter argues that this suggestion is in contradiction with previous demonstrations and with recent results that experimentally show the advantages of volume inversion. In replying, Venkatesan, et al., maintain that, while volume inversion could cause drain current enhancements in the near threshold region, it does not significantly affect the device characteristics in the strong inversion regime.<>
Keywords
insulated gate field effect transistors; semiconductor-insulator boundaries; drain current enhancements; dual gate operation; n-channel SOI MOSFET; near threshold region; strong inversion regime; volume inversion; Annealing; Electron devices; Electrostatics; Insulation; MOSFET circuits; Numerical simulation; Silicon on insulator technology; Threshold voltage; Transconductance; Virtual colonoscopy;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.192876
Filename
192876
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