An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date