Estimation of fault-free leakage current using wafer-level spatial information

Leakage current or the I/sub DDQ/ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is rising rapidly as semiconductor technology advances. This makes it difficult to distinguish between faulty and fault-free chips using traditional threshold setting methods. This paper presents a method to estimate leakage current using neighboring chip information on a wafer. Outlier chips are rejected, and a least-squares-fit plane through neighboring chips is used to estimate defect-free I/sub DDQ/. Chips that significantly deviate from the estimate are rejected. The proposed method is evaluated using industrial test data.