Programmable interleaver design for analog iterative decoders

Author

Gaudet, Vincent C. ; Gaudet, Rolland J. ; Gulak, P. Glenn

Author_Institution

Univ. of Toronto, Ont., Canada

Volume

49

Issue

7

fYear

2002

fDate

7/1/2002 12:00:00 AM

Firstpage

457

Lastpage

464

Abstract

Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of 100, as opposed to full crossbars, while maintaining full programmability.

Keywords

CMOS analogue integrated circuits; analogue processing circuits; error correction codes; interleaved codes; iterative decoding; programmable circuits; turbo codes; crossbar layers; error control codes; full programmability; interleaver size; iterative decoders; path capacitance; path resistance; programmable analog interleaver architectures; programming logic; static CMOS; switch count; transistor count; turbo codes; Capacitance; Circuits; Delay; Iterative algorithms; Iterative decoding; Logic programming; Random access memory; Silicon; Switches; Turbo codes;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/TCSII.2002.805022

Filename

1046045