100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technology

Author

Murata, Koichi ; Sano, Kimikazu ; Kitabayashi, Hiroto ; Sugitani, Suehiro ; Sugahara, Hirohiko ; Enoki, Takatomo

Author_Institution

NTT Photonics Labs., NTT Corp., Kanagawa, Japan

Volume

39

Issue

1

fYear

2004

Firstpage

207

Lastpage

213

Abstract

This paper describes the 100-Gb/s multiplexing operation of a selector IC and demultiplexing operation of a D-type flip-flop (D-FF) using production-level 0.1-μm-gate-length InP HEMT IC technology. To boost the operating speed of the selector IC, a selector core circuit directly drives an external 50-Ω load, and is included in the output stage. In addition, a test chip containing the selector and a D-FF to confirm error-free operation of these circuits was designed. The fabricated selector IC exhibited clear eye openings at 100 Gb/s, and its error-free operation was confirmed by using the test chip.

Keywords

HEMT integrated circuits; III-V semiconductors; demultiplexing equipment; field effect digital integrated circuits; flip-flops; high-speed integrated circuits; indium compounds; multiplexing equipment; optical communication equipment; 0.1-μ hboxm-gate-length InP HEMT IC technology; 100 Gbit/s; 50-Ω load; D-FF; D-type flip-flop; InP HEMT technology; demultiplexing IC operations; error-free operation; multiplexing IC operations; selector IC; selector core circuit; test chip; Circuit synthesis; Circuit testing; Clocks; Demultiplexing; Error-free operation; Flip-flops; HEMTs; Indium phosphide; Integrated circuit testing; Paper technology;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.820854

Filename

1261302