A dynamically reconfigurable SIMD processor for a vision chip

Author

Komuro, Takashi ; Kagami, Shingo ; Ishikawa, Masatoshi

Author_Institution

Graduate Sch. of Inf. Sci. & Technol., Univ. of Tokyo, Japan

Volume

39

Issue

1

fYear

2004

Firstpage

265

Lastpage

268

Abstract

Conventional SIMD image processors are very effective for early visual processing because of their parallelism. However, in performing more advanced processing, they exhibit some problems, such as poor performance in global operations and a tradeoff between flexibility of processing and the number of pixels. This paper shows a new architecture and sample algorithms of a vision chip that has the ability to reconfigure its hardware dynamically by chaining processing elements. A prototype chip with 64×64 pixels manufactured using the 0.35-μm CMOS process is also shown.

Keywords

CMOS integrated circuits; computer vision; digital signal processing chips; image processing equipment; parallel architectures; reconfigurable architectures; 0.35 micron; 64 pixels; CMOS process; SIMD image processors; chaining processing elements; dynamically reconfigurable architecture; hardware reconfiguration; parallelism; processing flexibility; prototype chip; vision chip; visual processing; CMOS process; Flexible printed circuits; Hardware; Image processing; Manufacturing processes; Parallel processing; Pixel; Process control; Prototypes; Shift registers;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.820876

Filename

1261313