• DocumentCode
    864120
  • Title

    Scan cell design for launch-on-shift delay tests with slow scan enable

  • Author

    Xu, G. ; Singh, A.D.

  • Author_Institution
    Electr. & Comput. Eng. Dept., Auburn Univ., AL
  • Volume
    1
  • Issue
    3
  • fYear
    2007
  • fDate
    5/1/2007 12:00:00 AM
  • Firstpage
    213
  • Lastpage
    219
  • Abstract
    Most scan-based designs implement the scan enable as a slow speed global control signal, and can therefore only implement launch-on-capture (LOC) delay tests. Launch-on-shift (LOS) tests are generally more effective, achieving higher fault coverage with significantly fewer test vectors, but requiring a fast scan enable. A low cost solution for implementing LOS tests by adding a small amount of logic in each flip-flop to align the slow scan enable signal to the clock edge is presented. The new design is much more efficient when compared with other recent proposals and can support full LOS testing. It can be further modified for mixed LOC/LOS tests that achieve transition delay fault coverage approaching 95% for the ISCAS89 benchmarks
  • Keywords
    clocks; delay circuits; flip-flops; integrated circuit design; integrated circuit testing; clock edge; flip-flops; global control signal; launch-on-capture delay tests; launch-on-shift delay tests; scan cell design; slow scan enable; transition delay fault coverage;
  • fLanguage
    English
  • Journal_Title
    Computers & Digital Techniques, IET
  • Publisher
    iet
  • ISSN
    1751-8601
  • Type

    jour

  • Filename
    4205037