• DocumentCode
    86518
  • Title

    3-D WiRED: A Novel WIDE I/O DRAM With Energy-Efficient 3-D Bank Organization

  • Author

    Thakkar, Ishan ; Pasricha, Sudeep

  • Author_Institution
    Colorado State Univ., Fort Collins, CO, USA
  • Volume
    32
  • Issue
    4
  • fYear
    2015
  • fDate
    Aug. 2015
  • Firstpage
    71
  • Lastpage
    80
  • Abstract
    WIDE I/O DRAM is a promising 3-D memory architecture for low-power/highperformance computing. This paper proposes a new WIDE I/O DRAM architecture to reduce access latency and energy consumption at the same time, which shows the possibility of further optimization of the WIDE I/O DRAM architecture and the impact of TSV usage in the memory architecture on the performance and energy consumption.
  • Keywords
    DRAM chips; memory architecture; optimisation; 3D WiRED; 3D memory architecture; TSV usage; energy-efficient 3D bank organization; low-power high performance computing; novel WIDE I/O DRAM; Computer architecture; DRAM chips; Electric breakdown; Energy efficiency; Parallel processing; Random access memory; 3D-DRAM; Wide I/O; energy-efficiency;
  • fLanguage
    English
  • Journal_Title
    Design & Test, IEEE
  • Publisher
    ieee
  • ISSN
    2168-2356
  • Type

    jour

  • DOI
    10.1109/MDAT.2015.2440411
  • Filename
    7116520