Selection of the Optimal Memory Configuration in a System Affected by Soft Errors

The selection of the best memory configuration is a challenge for designers when systems are affected by soft errors. When memory reliability is an issue and scrubbing is not recommendable, multibit protection codes are one of the available options. In this paper, the reliability of memories protected with those codes is studied. First, a method to analytically approximate the mean number of events to failure of memories protected with error correction codes capable of handling multiple bit errors is presented and validated through simulation experiments. Then, the selection of the optimal protection code for a given memory configuration in terms of memory size, word length, and target reliability level is analyzed. This selection process is illustrated using a practical case study. The study is then extended to determine, for a given error correcting code, the maximum memory size that would meet a target reliability level. Finally, the effect of the memory word size on the system reliability is considered by comparing different options. In summary, the proposed methods can be useful for designers when choosing the memory configuration at the system level for critical applications in which reliability is a major concern.