A 16-bit multiflow concurrent processor for VTR control

Author

Minakuchi, H. ; Kunihira, T. ; Ohta, Y. ; Suehiro, K. ; Soga, J. ; Sakai, T. ; Ochi, T. ; Urade, M. ; Okamoto, T.

Author_Institution

Matsushita Electron. Corp., Nagaoka, Japan

Volume

34

Issue

3

fYear

1988

fDate

8/1/1988 12:00:00 AM

Firstpage

580

Lastpage

587

Abstract

A processor architecture is presented that uses a multiconcurrent processing loop consisting of multiple central processing units and processing instructions in a master-slave type relationship. Using this architecture, a 16-bit CMOS concurrent processor and software were developed for controlling a videotape recorder (VTR). This single-chip system provides concurrent actuation of various motors and system control of the VTR. The processor IC is 5.6 mm by 6.8 mm, containing about 160000 digital and 1900 analog elements. It is configured as a 76-pin DIP (dual in-line package) with a typical power consumption of 120 mW.

Keywords

CMOS integrated circuits; microprocessor chips; parallel processing; telecommunications computer control; video tape recorders; 120 mW; 16 bit; 76-pin DIP; CMOS concurrent processor; VTR control; dual in-line package; master-slave type relationship; motors; multiconcurrent processing loop; multiflow concurrent processor; multiple central processing units; power consumption; processing instructions; processor IC; processor architecture; single-chip system; software; system control; videotape recorder; Analog integrated circuits; CMOS process; Central Processing Unit; Computer architecture; Control systems; Digital integrated circuits; Electronics packaging; Master-slave; Process control; Video recording;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.20157

Filename

20157