100-Mhz 1000-bit ultrasonic digital delay-line time-compression store

Digital information is stored in a recirculating loop that consists of an otc glass delay line and associated circuitry operating in the 100mhz range. A maximum retiming margin of 67 % was observed. The circuitry is designed to use only those components that can be implemented using integrated-circuit technology; all critical tolerances are related to component parameter ratios. A minimum retiming margin of 54 % is expected for typical ic tolerances. The economical advantages of operating the loop at 100 mhz, the size of the store, and the 1000-bits storage capacity can be retained at considerably lower external bit rates if sequential bit locations are accessed only one per n recirculation cycles (n=1,2,3,...). This generalized deltic access mode has potential use in speed converting buffer stores between fast computer processors and slower peripheral data-processing devices.