DocumentCode
870589
Title
Utilizing a Multiprocessor Architecture - The Performance of MIDAS
Author
Maples, Creve ; Weaver, Daniel ; Meng, John ; Rathbun, William ; Logan, Douglas
Author_Institution
Lawrence Berkeley Laboratory, University of California Berkeley, California 94720
Volume
30
Issue
5
fYear
1983
Firstpage
3827
Lastpage
3832
Abstract
The MIDAS architecture organizes multiple CPUs into clusters called distributed subsystems. Each subsystem consists of an array of processors controlled by a supervisory CPU. The multiprocessor array is composed of commercial CPUs (with floating point hardware) and specialized processing elements. Interprocessor communication within the array may occur either through switched memory modules or common shared memory. The architecture permits multiple processors to be focused on single problems. A distributed subsystem has been constructed and tested. It currently consists of a supervisor CPU; 16 blocks of independently switchable memory; 9 general purpose, VAX-class CPUs; and 2 specialized pipelined processors to handle I/O. Results on a variety of problems indicate that the subsystem performs 8 to 15 times faster than a standard computer with an identical CPU. The difference in performance represents the effect of differing CPU and I/O requirements.
Keywords
Application software; Communication switching; Communication system control; Computer architecture; Data analysis; Hardware; Laboratories; Nuclear physics; Pipelines; Process control;
fLanguage
English
Journal_Title
Nuclear Science, IEEE Transactions on
Publisher
ieee
ISSN
0018-9499
Type
jour
DOI
10.1109/TNS.1983.4333019
Filename
4333019
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