The Logarithmic Tunnel Diode Amplifier

This paper describes design techniques and performance characteristics of a high-frequency logarithmic amplifier. The technique used is to sum the detected outputs of each amplifier in a cascade in order to generate a straight line segment approximation to the desired logarithmic responses. It is shown that the normal RF characteristics of tunnel diode amplifiers approximate this performance when operated at minimum negative resistance. A 3.05 GHz tunnel diode amplifier is designed using these principles, and its performance is described in this paper. It is shown that the amplifier has an experimental error of /spl plsmn/0.625 dB over a compression range of 60 dB input signal power.