DocumentCode
872039
Title
Designing systolic arrays using digit-serial arithmetic
Author
Corbett, Peter ; Hartley, Richard
Author_Institution
Thomas J. Watson Res. Lab., Yorktown Heights, NY, USA
Volume
39
Issue
1
fYear
1992
fDate
1/1/1992 12:00:00 AM
Firstpage
62
Lastpage
65
Abstract
A method of transforming systolic arrays using bit-parallel arithmetic into arrays using digit-serial arithmetic is described. Digit-serial computation is an area-time efficient method of doing high-speed arithmetic calculations, having the advantage through appropriate choice of digit and word size of allowing throughput capacity to be matched to design needs. For a certain class of systolic arrays, digit-serial arithmetic allows a further very significant benefit by transforming arrays in which processors are under-utilized into arrays late with 100% processor utilization
Keywords
digital arithmetic; systolic arrays; area-time efficient method; bit-parallel arithmetic; digit-serial arithmetic; high-speed arithmetic calculations; systolic arrays; Arithmetic; Clocks; Concurrent computing; Fault tolerance; Hardware; Pipelines; Process design; Synchronization; Systolic arrays; Throughput;
fLanguage
English
Journal_Title
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1057-7130
Type
jour
DOI
10.1109/82.204111
Filename
204111
Link To Document