Parameterized SPICE subcircuits for multilevel interconnect modeling and simulation

Author

Chang, Keh-Jeng ; Chang, Norman H. ; Oh, Soo-Young ; Lee, Keunmyung

Author_Institution

Hewlett-Packard Co., Palo Alto, CA, USA

Volume

39

Issue

11

fYear

1992

fDate

11/1/1992 12:00:00 AM

Firstpage

779

Lastpage

789

Abstract

The authors describe a parameterized interconnect model library generator that provides VLSI designers with a direct link between numerical method-based capacitance simulators and SPICE-like circuit simulators. As a result, interconnect parasitics are parameterized in a manner similar to the parameterization of transistors in SPICE. Therefore, the effort and time needed by circuit designers or EDA tools to prepare distributed multiline R, C SPICE decks for circuit simulations is drastically reduced

Keywords

SPICE; VLSI; circuit analysis computing; circuit layout CAD; integrated circuit technology; metallisation; packaging; SPICE subcircuits; VLSI; capacitance simulators; circuit simulations; interconnect parasitics; model library generator; multilevel interconnect modeling; parameterized interconnect; Capacitance; Circuit simulation; Companies; Coupling circuits; Driver circuits; Integrated circuit interconnections; Laboratories; Libraries; SPICE; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1057-7130

Type

jour

DOI

10.1109/82.204126

Filename

204126