• DocumentCode
    873584
  • Title

    Bias polarity dependent effects of P+floating gate EEPROMs

  • Author

    Kuo, Charles ; King, Tsu-Jae ; Hu, Chenming

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
  • Volume
    51
  • Issue
    2
  • fYear
    2004
  • Firstpage
    282
  • Lastpage
    285
  • Abstract
    EEPROM devices with either N-type or P-type floating gate were fabricated and characterized. Program/erase speeds and stress-induced leakage current-related retention characteristics for both types of devices are explained. Discrepancies between previously published reports on P-type floating gate devices and PMOS gate current measurements are resolved. The feasibility of integrating P-type floating gate EEPROMs in high density memory arrays is examined.
  • Keywords
    EPROM; MOS integrated circuits; bipolar memory circuits; polar semiconductors; EEPROM devices; N-type floating gate; P-floating gate EEPROM; P-type floating gate; PMOS gate current measurements; bias polarity dependent effects; high density memory arrays; program/erase speeds; retention characteristics; stress-induced leakage current; Boron; Current measurement; EPROM; Lead compounds; Leakage current; Nonvolatile memory; Semiconductor memory; Tail; Technology forecasting; Tunneling;
  • fLanguage
    English
  • Journal_Title
    Electron Devices, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9383
  • Type

    jour

  • DOI
    10.1109/TED.2003.821702
  • Filename
    1262659
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=873584