DocumentCode
874017
Title
A complementary driver with a subnanosecond rise time
Author
Pierce, J.F.
Volume
4
Issue
5
fYear
1969
Firstpage
293
Lastpage
295
Abstract
A circuit specifically designed as a complementary driver for a high- speed scaling circuit is described. This circuit incorporates the principle of time-delayed negative feedback by using a passive delay line in the feedback path. The delay line provides optimum positioning of the bias voltage at the base of the nondriven transistor in a current-mode pair.
Keywords
Delay lines; delay lines; Delay lines; Diodes; Driver circuits; Feedback circuits; Large scale integration; Negative feedback; Propagation delay; Switches; Testing; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1969.1050020
Filename
1050020
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