A two-terminal transistor memory cell using breakdown

The features of the cell include easy fabrication, small cell area, large output signals, high-speed Read and Write capability, low average power and inherent immunity to small voltage perturbations. The storage time of the cell is determined by reverse-bias junction leakage and is greater than 10 ns at room temperatures for typical devices. Breakdown degradation of transistors is discussed and a memory fabrication scheme that avoids this degradation is suggested. Some early experimental results are mentioned.