A two-phase plasma-coupled static shift register

In designing an experimental 2-bit plasma-coupled shift register, fabricated with standard bipolar technology, it is shown that a simplification of the existing plasma-coupled device (PCD) concept by omission of the double base diode not only decreases the power dissipation and increases the ease of fabrication, but also increases the attractive simplicity of the basic cell. The average power dissipation of the new device is 200 /spl mu/W/bit at a clock frequency of 3 MHz. The bit density is 135 bit/mm/SUP 2/ with 10-/spl mu/m spacing between interconnection lines 10 /spl mu/m in width. A hypothetical layout with dielectric isolation and closer tolerances results in a bit density of 900 bit/mm/SUP 2/ and an estimated power dissipation of 80 /spl mu/W/bit.