A byte organized NMOS/CCD memory with dynamic refresh logic

Author

Varshney, Ramesh C. ; Guidry, Mark R. ; Amelio, Gilbert F. ; Early, James M.

Volume

11

Issue

1

fYear

1976

Firstpage

18

Lastpage

24

Abstract

A 9216 bit NMOS/CCD memory organized as 1024 words by 9 bits is described. It employs a buried channel two phase charge-coupled device (CCD) storage cell combined with n-channel silicon gate Isoplanar (TM) MOS technology for logic functions and TTL compatible interfacing. Techniques of charge detection by using internally generated reference voltages are detailed. A low noise CCD input writing scheme and a dynamic sense-refresh cell are described. Input-output logic is given that permits operating modes of read, write, read-modify-write, and recirculate. Operation at the specification limits of 100 kHz and 2 MHz is shown.

Keywords

Charge-coupled devices; Digital integrated circuits; Monolithic integrated circuits; Semiconductor storage devices; charge-coupled devices; digital integrated circuits; monolithic integrated circuits; semiconductor storage devices; Capacitive sensors; Charge coupled devices; High performance computing; Logic circuits; Logic devices; MOS devices; Random access memory; Research and development; Shift registers; Solid state circuits;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1976.1050670

Filename

1050670