Optimal UTB FD/SOI device structure using thin BOX for sub-50-nm SRAM design

Author

Mukhopadhyay, Saibal ; Kim, Keunwoo ; Wang, Xinlin ; Frank, David J. ; Oldiges, Philip ; Chuang, Ching-Te ; Roy, Kaushik

Author_Institution

Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

Volume

27

Issue

4

fYear

2006

fDate

4/1/2006 12:00:00 AM

Firstpage

284

Lastpage

287

Abstract

In this letter, the random dopant fluctuation effect in ultrathin-body (UTB) fully depleted/silicon-on-insulator (FD/SOI) devices is analyzed. We show that due to larger variability and asymmetry in threshold voltage V_t distribution, it will be difficult to use UTB FD/SOI devices for sub-50-nm static random access memory (SRAM) design. Using thinner buried oxide (BOX) FD/SOI devices, the asymmetry in the V_t spread can be reduced. We present a viable concept of FD/SOI SRAM and predict that a thin-BOX device is the optimal FD/SOI structure for SRAM in sub-50-nm technology nodes.

Keywords

SRAM chips; buried layers; doping profiles; nanoelectronics; semiconductor devices; semiconductor doping; silicon-on-insulator; random dopant fluctuation effect; silicon-on-insulator devices; static random access memory design; thin buried oxide device; threshold voltage distribution; ultrathin-body fully depleted devices; Circuit stability; Doping; Fluctuations; Random access memory; Resource description framework; Robustness; SRAM chips; Silicon on insulator technology; Threshold voltage; Very large scale integration; Fully depleted silicon-on-insulator (SOI); leakage; performance; random dopant fluctuations (RDFs); stability; static random access memory (SRAM);

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2006.871540

Filename

1610787