DocumentCode
882213
Title
Variable V CC design techniques for battery-operated DRAMs
Author
Yoo, Seung-Moon ; Haq, Ejaz ; Lee, Seung-Hoon ; Choi, Yun-Ho ; Cho, Soon-In ; Kang, Nam-Soo ; Chin, Daeje
Author_Institution
Samsung Electronics Co. Ltd., Kyungki-Do, South Korea
Volume
28
Issue
4
fYear
1993
fDate
4/1/1993 12:00:00 AM
Firstpage
499
Lastpage
503
Abstract
Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V CC level; (2) compensation of DC generators, V BB and V PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation
Keywords
CMOS integrated circuits; DRAM chips; compensation; reference circuits; 1.8 to 3.6 V; 16 Mbit; 50 ns; DC generators; DRAMs; NiCd; alkaline batteries; battery-operated; compensation; dynamic RAM; latch-isolation sense amplifier; low-voltage reference generator; static word-line driver; variable VCC design techniques; variable self-refresh scheme; Batteries; Costs; DC generators; Detectors; Driver circuits; Manufacturing processes; Portable computers; Random access memory; Timing; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.210034
Filename
210034
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