DocumentCode
882465
Title
A 16 384-bit dynamic RAM
Author
Ahlquist, C.Norman ; Breivogel, Joseph R. ; Koo, James T. ; McCollum, John L. ; Oldham, William G. ; Renninger, Alan L.
Volume
11
Issue
5
fYear
1976
Firstpage
570
Lastpage
574
Abstract
A 16-kbit dynamic RAM is described which is TTL compatible on all pins, and fits a standard 16-pin package. A single-transistor storage cell is used which occupies 455 /spl mu/m/SUP 2/. The device is fabricated in n-channel two-layer polysilicon gate technology using conventional design rules. The chip size is 145 by 234 mils. A low-power sense amplifier is used for each 64 memory cells. A special refresh mode is possible in which all 256 sense amplifiers are active, and the entire memory can be refreshed in 64 address cycles.
Keywords
Digital integrated circuits; Monolithic integrated circuits; Random-access storage; Semiconductor storage devices; digital integrated circuits; monolithic integrated circuits; random-access storage; semiconductor storage devices; Circuits; Clocks; Content addressable storage; DRAM chips; Packaging; Pins; Random access memory; Read-write memory; Silicon;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1976.1050783
Filename
1050783
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