• DocumentCode
    883023
  • Title

    Double ion implanted V-MOS technology

  • Author

    Ou-Yang, Paul

  • Volume
    12
  • Issue
    1
  • fYear
    1977
  • fDate
    2/1/1977 12:00:00 AM
  • Firstpage
    3
  • Lastpage
    9
  • Abstract
    An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 μm) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-Å gate oxide thickness.
  • Keywords
    Digital integrated circuits; Field effect integrated circuits; Ion implantation; Large scale integration; digital integrated circuits; field effect integrated circuits; ion implantation; large scale integration; Electron mobility; Fabrication; Impurities; Ion implantation; Large scale integration; MOS devices; MOSFET circuits; Substrates; Threshold voltage; Voltage control;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1977.1050833
  • Filename
    1050833