Strained-Si Channel Super-Self-Aligned Back-Gate/Double-Gate Planar Transistors

Author

Lin, Hao ; Liu, Haitao ; Kumar, Ajit ; Avci, Uygar ; Van Delden, Jay S. ; Tiwari, Sandip ; Kumar, Ajit

Author_Institution

Sch. of Appl. & Eng. Phys., Cornell Univ., Ithaca, NY

Volume

28

Issue

6

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

506

Lastpage

508

Abstract

We present a reproducible approach to the fabrication of super-self-aligned back-gate/double-gate n-channel and p-channel transistors with thin silicon channels and thick source/drain polysilicon regions. The device structure provides capability for scalable control of channel electrostatics, threshold variability without sacrificing source/drain series resistance, and capability of introducing strain to improve carrier transport. The separate device, circuit, and functional level back-gate access that is available through bottom interconnection also provides capability for adaptive power control and novel circuit design. Both n-channel and p-channel devices are demonstrated with the threshold tuning capability

Keywords

MOSFET; silicon; Si; adaptive power control; back-gate access; buried interconnect; carrier transport; channel electrostatics; field-effect transistor; n-channel transistor; p-channel transistor; source/drain series resistance; strained-Si channel planar transistors; super-self-aligned back-gate/double-gate planar transistors; thick source/drain polysilicon regions; thin silicon channels; threshold tuning capability; threshold variability; Adaptive control; Capacitive sensors; Circuit synthesis; Electrostatics; Fabrication; Integrated circuit interconnections; Power control; Programmable control; Silicon; Strain control; Adaptive power control; back-gate/double-gate field-effect transistor (FET); buried interconnect; strained-Si channel; super-self-alignment;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2007.896896

Filename

4212179