DocumentCode
886005
Title
VMOS technology applied to dynamic RAMs
Author
Hoffmann, Kurt ; Losehand, Reinhard
Volume
13
Issue
5
fYear
1978
fDate
10/1/1978 12:00:00 AM
Firstpage
617
Lastpage
622
Abstract
A seven-mask VMOS process has been developed for dynamic RAMs with self-aligned VMOS and planar Al-gate transistors. Using 4 μm photolithography, one-transistor cells with a cell size of 150 μm/SUP 2/ have been realized. The read signal at the bit line is more than 200 mV. Implementations of a sense amplifier and a word-line driver show that those circuits determine the smallest word and bit line spacing. The paper is concluded by a proposal for a 64K RAM with a chip size of 21 mm/SUP 2/ using 4 μm design rules.
Keywords
Field effect integrated circuits; Integrated circuit technology; Integrated memory circuits; Large scale integration; Random-access storage; field effect integrated circuits; integrated circuit technology; integrated memory circuits; large scale integration; random-access storage; DRAM chips; Driver circuits; Etching; Lithography; Oxidation; Proposals; Protection; Random access memory; Read-write memory; Subthreshold current;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1978.1051109
Filename
1051109
Link To Document