Word-line architecture for highly reliable 64-Mb DRAM

Author

Takashima, Daisaburo ; Oowaki, Yukihito ; Ogiwara, Ryu ; Watanabe, Yohji ; Tsuchida, Kenji ; Ohta, Masako ; Nakano, Hiroaki ; Watanabe, Shigeyoshi ; Ohuchi, Kazunori

Author_Institution

Toshiba Corp., Kawasaki, Japan

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

603

Lastpage

609

Abstract

A unique word-line voltage control method for the 64-Mb DRAM and beyond is proposed. It realizes a constant lifetime for a thin gate oxide. This method controls word-line voltage and compensates reliability degradation in the thin gate oxide for cell-transfer transistors. It keeps the time-dependent dielectric breakdown (TDDB) lifetime constant under any conditions of gate oxide thickness fluctuation, temperature variation, and supply voltage variation. This method was successfully implemented in a 64-Mb DRAM to realize high reliability. This chip achieved a 10⁵ times reliability improvement and a 0.3~1.8-V larger word-line voltage margin to write ONE data into the cell

Keywords

DRAM chips; MOS integrated circuits; circuit reliability; memory architecture; 64 Mbit; DRAM; cell-transfer transistors; constant TDDB lifetime; dynamic RAM; high reliability; oxide thickness fluctuation; reliability degradation compensation; supply voltage variation; temperature variation; thin gate oxide; time-dependent dielectric breakdown; word line architecture; word-line voltage control; Breakdown voltage; Degradation; Dielectric breakdown; Fluctuations; Helium; Leakage current; Random access memory; Threshold voltage; Ultra large scale integration; Voltage control;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126550

Filename

126550