Temperature-compensation circuit techniques for high-density CMOS DRAMs

Author

Min, Dong-Sun ; Cho, Sooin ; Jun, Dong Soo ; Lee, Dong-Jae ; Seok, Yongsik ; Chin, Daeje

Author_Institution

Samsung Electron. Co. Ltd., Kyungki-Do, South Korea

Volume

27

Issue

4

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

626

Lastpage

631

Abstract

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/°C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/°C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques

Keywords

CMOS integrated circuits; DRAM chips; compensation; convertors; 16 Mbit; CMOS DRAM; RC-delay circuit; back-bias generator; high-density; internal voltage converter; latchup immunity; temperature compensation circuit techniques; BiCMOS integrated circuits; CMOS memory circuits; CMOS process; CMOS technology; Circuit synthesis; MOSFETs; Photonic band gap; Random access memory; Temperature dependence; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.126553

Filename

126553