Dose-Rate Upset Patterns in a 16K CMOS SRAM

Dose-rate LINAC tests have been performed on the Sandia National Laboratories SA3240 16k CMOS SRAM and transient radiation induced upset patterns are presented. These patterns indicate a progression of upsets across the memory array with increasing doserate, as predicted by computer simulations of the rail span collapse effect. The upset bitmap patterns and simulation results show that VDD power supply bussing is not critical, or even necessary, for radiation hardened CMOS epitaxial parts if local VDD taps to a powered substrate are used; the critical factor is the efficiency of the VSS bussing scheme. The effects of initial storage patterns and total ionizing dose on the upset patterns are also presented.