• DocumentCode
    887219
  • Title

    Modeling of the diode input I/sup 2/L structure

  • Author

    Perlegos, Gust ; Chan, Shu-Park

  • Volume
    14
  • Issue
    3
  • fYear
    1979
  • fDate
    6/1/1979 12:00:00 AM
  • Firstpage
    645
  • Lastpage
    648
  • Abstract
    A high-speed single-collector multiinput Schottky diode I/SUP 2/L structure is presented. The structure features negligible p-n-p and a relatively low extrinsic base minority carrier storage, and lends to the near elimination of saturation. A theoretical model predicts that the structure produces circuit delays of better than 3 ns at 50 /spl mu/A.
  • Keywords
    Bipolar integrated circuits; Integrated logic circuits; Schottky-barrier diodes; Semiconductor device models; bipolar integrated circuits; integrated logic circuits; semiconductor device models; Circuits; Current density; Differential equations; Electrons; Impurities; Logic; Microprocessors; Propagation delay; Schottky diodes; Voltage;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1979.1051230
  • Filename
    1051230
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=887219