• DocumentCode
    887419
  • Title

    Retention testing of MNOS LSI memories

  • Author

    Jeppson, Kjell O. ; Svensson, Christer M.

  • Volume
    14
  • Issue
    4
  • fYear
    1979
  • fDate
    8/1/1979 12:00:00 AM
  • Firstpage
    723
  • Lastpage
    729
  • Abstract
    User-oriented test methods for MNOS LSI memories with built-in test modes have been developed. Their application is demonstrated on the commercial ER3401 memory. The memory retention is evaluated in two cases-the static retention time in power-down or in stand-by and the read retention during repeated reading, i.e., the maximum number of read cycles. In the first case, the two loss mechanisms, tunneling and thermal excitation of stored charge are evaluated separately and their influence is combined. In the second case, the limiting mechanism is slow writing by the read signal. On bases of these investigations, a static retention time of 60 yr at 70°C and 2 yr at 125°C is predicted and a read retention of 3×10/SUP 11/ read cycles at 70°C and 2×10/SUP 9/ cycles at 125°C is found for the ER3401.
  • Keywords
    Field effect integrated circuits; Integrated circuit testing; Integrated memory circuits; Large scale integration; field effect integrated circuits; integrated circuit testing; integrated memory circuits; large scale integration; Built-in self-test; Circuit testing; Helium; Laboratories; Large scale integration; Logic circuits; Monte Carlo methods; Predictive models; Signal processing algorithms; Temperature;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1979.1051250
  • Filename
    1051250