High Density Integrated Computing Circuitry with Multiple Valued Logic

It is well known that multiple valued logic can theoretically provide a greater logical packing density than binary logic. In this correspondence, a useful quatemary logic arithmetic circuit is discussed in its combinational and synchronous sequential forms. The results of applying this circuit in proposed implementations of digital parallel counters are then compared to all-binary designs. A significant savings in integrated devices and thus increased packing density could be obtained in each case.