DocumentCode
891205
Title
Design and Use of Fault Simulation for Saturn Computer Design
Author
Hardie, Fred H. ; Suhocki, Robert J.
Author_Institution
IBM Federal Systems Division, Electronics Systems Center, Owego, N. Y.
Issue
4
fYear
1967
Firstpage
412
Lastpage
429
Abstract
A system of IBM 7090 Data Processing System computer programs was developed for the purpose of normal and/or fault simulation of the Saturn computer. This paper will describe the design of the simulator and cite several applications in the development of the Saturn computer. The architecture, plus several important characteristics of the simulator, are presented. These include the Design Automation input interface, the logic selection procedure, failure injection, the compilation procedure, logical simulation and functional simulation. The ability to simulate up to 4000 Saturn instructions in either normal and/or fault environments (up to 33 faults per IBM 7090 run) will be demonstrated. Simulation of single, multiple, solid or intermittent faults, plus an automated statistical analysis of intermittent fault simulation results, will be presented. The IBM 7090 execution time of a compiled logic simulator can be prohibitive. To minimize running time several programming techniques were utilized, including logic block ordering (to allow single pass simulation), parallel fault simulation, stimulus bypassing, and functional simulation. These techniques are described. Several special forms of simulator output were developed. The use of this output and the applications of the simulator are presented, including design verfication, test program evaluation, generation of a test point catalog, disagreement detector network evaluation, disagreement detector placement, intermittent failure analysis.
Keywords
Analytical models; Application software; Computational modeling; Computer simulation; Data processing; Detectors; Logic programming; Saturn; Solid modeling; Testing; Design verification; Saturn computer; Saturn disagreement detection; Saturn voting; diagnostic program checkout; fault simulation; intermittent fault analysis; simulation; triple modular redundancy;
fLanguage
English
Journal_Title
Electronic Computers, IEEE Transactions on
Publisher
ieee
ISSN
0367-7508
Type
jour
DOI
10.1109/PGEC.1967.264644
Filename
4039105
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