A 1.5 Gb/s 8×8 cross-connect switch using a time reservation algorithm

Author

Matsunaga, Haruhiko ; Uematsu, Hitoshi

Author_Institution

NTT Transmission Syst. Lab., Kanagawa, Japan

Volume

9

Issue

8

fYear

1991

fDate

10/1/1991 12:00:00 AM

Firstpage

1308

Lastpage

1317

Abstract

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s

Keywords

ISDN; bipolar integrated circuits; broadband networks; electronic switching systems; pipeline processing; queueing theory; time division multiplexing; 1.5 Gbit/s; ATM; B-ISDN; Si bipolar process; asynchronous transfer mode; contention resolution; contention-resolution module LSI; cross-connect switch; high-speed; input buffer controller LSI; input queuing type switching architecture; large-capacity; maximum port speed; pipeline processing; space-division switching LSI; time reservation algorithm; time scheduling; Asynchronous transfer mode; Computer architecture; Large scale integration; Pipeline processing; Processor scheduling; Scheduling algorithm; Switches; Switching circuits; Throughput; Velocity measurement;

fLanguage

English

Journal_Title

Selected Areas in Communications, IEEE Journal on

Publisher

ieee

ISSN

0733-8716

Type

jour

DOI

10.1109/49.105177

Filename

105177