A 256 kbit ROM with serial ROM cell structure

The realization of a 256 kbit ROM using a 500 /spl Aring/ E/D NMOS technology is described. A high packaging density has been achieved by using a NAND structure in the memory array and in the decoders. Some characteristics of this serial ROM structure are discussed and compared with the conventional parallel configurations. The 32K/spl times/8 bit ROM with a bit size of 5.25/spl times/5.5 /spl mu/m/SUP 2/ has a total chip area of 18.6 mm/SUP 2/. Operating from a single 5 V supply, the device has a typical access time of 850 ns with a minimum cycle time of 1500 ns and dissipates 70 mW. In the power-down mode this power is reduced to 5 mW.