Prediction of error probabilities for integrated digital synchronizers

Synchronization errors occur when asynchronous digital signals are received by clocked digital systems. Digital synchronizers are designed to minimize the probability of such errors. Empirical determination of error probabilities, as used in the past, is not a viable method for large-scale integrated circuit because it is cumbersome, interferes with the circuit performance, and does not account for tolerances of circuit parameters. The authors describe a complete method for predicting synchronization-error probabilities using circuit simulation and theoretical analysis. The analysis includes the efforts of random noise. The simulation model readily takes into account tolerances of the circuit parameters. The direct observability of all parameters of the model enhances the understanding of the synchronization process and the reliability of the predictions.