A 300K transistor NMOS peripheral processor

The circuit and the design of an experimental 16-bit peripheral processor are described. The circuit is used in controller applications between mass storage memories and the CPU of mainframes. The chip is fabricated in 2-/spl mu/m NMOS technology using polycide and 2 metal layers. This component (300000 transistors, 105 mm/SUP 2/, 152 pins) handles data rates up to 5 Mb/s and has a power dissipation of about 2 W. A highly modular and regular design and some automatically generated layouts resulted in a short design time. The top-down design required intensive floorplanning. Outstanding features are the function slice microinstruction decoding scheme and a large on-chip microprogram RAM with 36 kbits.