• DocumentCode
    898260
  • Title

    A generalized layout rule generator

  • Author

    Sugino, Mike ; Akera, L.A.

  • Volume
    20
  • Issue
    2
  • fYear
    1985
  • fDate
    4/1/1985 12:00:00 AM
  • Firstpage
    589
  • Lastpage
    591
  • Abstract
    As VLSI fabrication processes and systems become more complex, the number of layout rules required increases dramatically. A program is described that automatically creates and evaluates layout rules. The layout rules for a submicrometer CMOS process are generated and the variation of the density of a CMOS static RAM cell with process changes is illustrated.
  • Keywords
    CMOS integrated circuits; Circuit layout CAD; Integrated circuit technology; VLSI; circuit layout CAD; integrated circuit technology; CMOS process; Computational modeling; Delay effects; Distributed computing; Flexible printed circuits; MOS devices; Particle measurements; Random access memory; Size measurement; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1985.1052348
  • Filename
    1052348
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=898260