Power-aware design method for class A switched-current wave filters

Power consumption is addressed in switched-current filters, designed using the wave filter technique and class A memory cells. It has been demonstrated that power consumption can be reduced through the proposed two-stage bias and signal current scaling method, whilst ensuring no degradation in filter total harmonic distortion. Two full transistor-level filter case studies using 0.6 μm 3.3 V BSim3v3 CMOS foundry models are given to demonstrate the method, with additional simulation results for filters of different types and orders showing power savings as high as 16.6%. One case study has been fabricated, with measured silicon results confirming power savings using the proposed method.