Observation of latch-up phenomena in CMOS ICs by means of digital differential voltage contrast

The latch-up phenomenon in CMOS ICs is studied by means of a SEM observation technique that is based on capacitively coupled voltage contrast and is characterized by digital beam control and image acquisition. Passivated devices are studied at low beam energies, without interfering with their electrical behavior. The comparison between images taken in the latched and nonlatched state allows reliable identification of the latch-up current paths and thus of the latched site. The performance of the technique is demonstrated by three examples which refer to one standard and two custom CMOS ICs.