The design of TSC error C/D circuits for SEC/DED codes

Author

Gaitanis, Nicolaos

Author_Institution

Dept of Comput., NRC Democritos, Athens, Greece

Volume

37

Issue

3

fYear

1988

fDate

3/1/1988 12:00:00 AM

Firstpage

258

Lastpage

265

Abstract

A design technique for totally self-checking (TSC) error correcting/detection (C/D) circuits of single error correcting, double error detection (SEC/DED) codes is described. The structure of these circuits achieves concurrent fault detection and location under normal input conditions. A separate internal fault indication is provided. This improves the reliability, maintainability, and availability of the entire fault-tolerant system because faults are repaired before the appearance of input errors. The error C/D circuits are composed of TSC error detectors, error locators, and error correctors. These circuits are two-rail TSC checkers and are designed using an algebraic approach

Keywords

automatic testing; error correction codes; error detection codes; fault tolerant computing; logic testing; availability; codes; concurrent fault detection; double error detection; error correction circuits; error detection circuits; error locators; fault-tolerant system; maintainability; reliability; single error correcting; totally self-checking; Circuit faults; Computer errors; Costs; Detectors; Electrical fault detection; Error correction; Error correction codes; Fault detection; Fault diagnosis; Maintenance;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.2162

Filename

2162