A 2-V amplitude-linear phase-locked loop

An amplitude-linear phase-locked loop which consumes less than 1 mW from a 2-V supply when operating at 100 kHz has been implemented in conventional 4-μm CMOS. Obtaining reliable MOS analog operation at low voltages constrains the circuit approaches available and forces large device geometries. Sample-data techniques are applied to realize a low-voltage CMOS equivalent to the bipolar multiplier, and a voltage-controlled oscillator control buffer is used to define a linear frequency characteristic. The measured performance demonstrates suitability for portable tone-decoding and FM demodulation applications.