DocumentCode
901721
Title
A self-testing 2-μm CMOS chip set for FFT applications
Author
Fox, John ; Surace, Giuseppe ; Thomas, Paul A.
Volume
22
Issue
1
fYear
1987
fDate
2/1/1987 12:00:00 AM
Firstpage
15
Lastpage
19
Abstract
A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)×(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-μm bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.
Keywords
CMOS integrated circuits; Cellular arrays; Digital arithmetic; Fast Fourier transforms; Multiplying circuits; VLSI; cellular arrays; digital arithmetic; fast Fourier transforms; multiplying circuits; Adders; Arithmetic; Built-in self-test; CMOS process; Design methodology; Hardware; Libraries; System testing; Throughput; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052665
Filename
1052665
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