Analysis of mesastable operation in RS CMOS flip-flops

An analysis of metastable operation in CMOS RS flip-flops is presented. An analytical formula for the flip-flop resolving time constant was derived using Shichman-Hodges model for NMOS and PMOS transistors. This formula, as related to the transistor dimensions, fabrication process parameters, and parasitic capacitance, uses proper transistor sizing to attain minimum flip-flop failure rate due to metastable operation. CMOS n-well, p-well, and twin-well flip-flop performance predicted analytically is also approved by SPICE level one simulation of transistor models. Real-time oscilloscope displays of metastable operation for two different CMOS RS flip-flop circuits are demonstrated.