DocumentCode
901927
Title
A configurable ROM circuit for use in gate arrays
Author
Ueda, Masahiro ; Sakashita, Kazuhiro ; Arakawa, Tawhiko ; Okazaki, Kaoru ; Asai, Sotoju ; Kuramitsu, Yuichi
Volume
22
Issue
1
fYear
1987
fDate
2/1/1987 12:00:00 AM
Firstpage
117
Lastpage
118
Abstract
A double word-line memory ROM (DWM-ROM) for use in gate arrays is described. It allows for an automatic layout by reducing the input pin count in the word lines by using two-step addressing. The advantage of this method has been verified by implementing a 16-bit microprocessor using an 8 K-gate array, based on a gate-isolated cell configuration, employing 1.5-μm double-metal CMOS technology. The 16-bit × 64-word ROM in the processor saves 30% of the transistor area due to the DWM-ROM.
Keywords
CMOS integrated circuits; Cellular arrays; Integrated logic circuits; Integrated memory circuits; Microprocessor chips; Read-only storage; cellular arrays; integrated logic circuits; integrated memory circuits; microprocessor chips; read-only storage; Automatic testing; Built-in self-test; CMOS technology; Decoding; Logic arrays; Logic testing; Programmable logic arrays; Read only memory; Solid state circuits; Very large scale integration;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052683
Filename
1052683
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