DocumentCode
902195
Title
Novel cell architecture for high performance digit-serial computation
Author
Aggoun, A. ; Ibrahim, M.K.
Author_Institution
Nottingham Univ., UK
Volume
29
Issue
11
fYear
1993
fDate
5/27/1993 12:00:00 AM
Firstpage
938
Lastpage
940
Abstract
A cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feedforward of the carry digit, which allows a high level of pipelining to increase the throughput rate. This will give designers greater flexibility in finding the best tradeoff between hardware cost and throughput rate. The effect of the number of pipelining levels on the throughput rate and hardware cost are presented.
Keywords
computer architecture; digital arithmetic; pipeline processing; carry digit; cell architecture; digit-serial computation; feedforward; hardware cost; pipelining levels; throughput rate;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19930625
Filename
216330
Link To Document