Measurement and modeling of short-channel MOS transistor gate capacitances

A flexible electrometer method for measuring the gate capacitances of small-geometry MOS transistors is described. This technique applies to standard test transistors requiring any on-chip circuitry. Subfemtofarad accuracy and high resolution (better than 0.1 fF) have been achieved. This technique permits flexibility with regard to choices of DC biases and test devices and provides a good means of monitoring capacitance changes in the device reliability studies. The measured gate capacitances show prominent short-channel effects. A short-channel MOS transistor capacitance model has been developed which takes into account the mobility-degradation effect, velocity-saturation effect, bias-dependent fringing-field effect, and source-drain series resistance effect. Good agreement between the measured and modeled results is found. This model can be easily modified for circuit-simulation applications.