A `missing neighbor model´ for capacitive loading in VLSI interconnect channels

The authors describe and justify a model of parasitic interconnect capacitance that enables the compilation of succinct numerical capacitance-per-unit-length tables for use in the parasitic extraction routines of layout and simulation software. The course of an interconnect line is divided into successive segments at planes where any parallel neighboring line begins or terminates. Parasitic capacitance is the sum of segment capacitances, each of which is found from a table entry appropriate to the local configuration of missing neighbor lines. Thus, CAD software with access to these tables and a routing database can accurately compute parasitic interconnection capacitance.